The invention generally relates to digital signal processing, and more particularly, to a multiplexed state saving analog-to-digital converter.
An analog-to-digital converter (ADC), such as a sigma delta modulator, provides a digital bit stream output of either single or multiple digital bits that are representative of an analog input signal. This bit stream output has noise that varies in the frequency domain, known as shaped noise. Shaped noise is typically removed by a digital low-pass filter having a cutoff frequency below the frequency where the shaped noise rises above the flat-band noise. Typically, the cutoff frequency is {fraction (1/16)}th to {fraction (1/64)}th of the converter sample rate.
FIG. 1 shows the functional architecture of a generic second-order, switched-capacitor, sigma delta modulator ADC similar to that described in U.S. Pat. No. 6,040,793, the contents of which are incorporated herein by reference. Input circuit 10 provides analog input signals for sampling, VinP and VinN. Subtracted from the input voltage signals are positive and negative feedback signals, RefP and RefN, from feedback circuit 11. The first stage integrator 12 receives the difference signals and provides an integrated output signal via coupling capacitor CS2 to second stage integrator 13. Each integrator 12 and 13 also has internal feedback capacitors, Ci1 and Ci2 respectively that feedback the integrated outputs to the integrator inputs. Thus, the voltage across these internal feedback capacitors Ci1 and Ci2 reflects the internal state of their associated integrators. The integrated outputs of each integrator 12 and 13 are provided via coupling capacitors CS31 and CS32 respectively to comparator 14. The output of comparator 14 is a digital data bitstream representative of the analog input voltages. This bitstream is supplied to a decimator filter (not shown) that reduces the out-of-band quantization noise component of the samples and generates a data stream of filtered output samples. A third-order sinc filter may be used, for example, in a particular ADC.
An ADC can be adapted to time division multiplex (TDM) between multiple input signals. Such a multiplexing ADC is described for example, in xe2x80x9cA Programmable Power Metering Chip,xe2x80x9d Y. M. Lin et al., Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, 1993, pp. 25.7.1-25.7.4, incorporated herein by reference. FIG. 2 in that article shows the multiplexed analog input and multiplexed digital filters following the modulator. Further description of such an approach is also provided in xe2x80x9cA Single Shot Sigma Delta Analog to Digital Converter for Multiplexed Applicationsxe2x80x9d; C. Lyden, et al, and U.S. Pat. Nos. 5,544,089; 5,345,236; and 5,627,536, all of which are incorporated herein by reference.
One specific application for a multiplexed ADC would be in an electrical power measuring device. In contemporary power distribution systems, the fundamental line frequency is typically 50 or 60 Hertz, but it should be appreciated that significant energy is present in harmonics as high as the 15th harmonic. The dynamic range requirements of an ADC are also formidable: 20 bits of digital resolution are needed to achieve an accuracy within 0.1% over a 1000:1 current range.
FIG. 2 shows an example of TDM of three input signals to an ADC with each analog input being selected for a processing period consisting of a fixed number of modulator samples before the multiplexer is switched to the next input waveform. In a power metering application, three voltage phases and three current phases need to be sampled. Thus, two three-channel multiplexed ADC modulators are sufficient. Each of the ADC modulators cycles through the same three inputs using the same time division to produce synchronized voltage-current sample pairs for each phase being measured. The separate phases are not themselves synchronized, of course, and are skewed in time from each other. This does not present a problem because the total three-phase power used for energy calculation is an arithmetic sum of the three individual power values.
Existing methods of multiplexing multiple analog inputs to a sigma delta modulator require drastically reducing the resulting sampled data rate. The sample rate of the final de-multiplexed output, Fmux, is the fastest rate possible from a multiplexed ADC with a successive approximation register-type (SAR) architecture. In contemporary systems, Fmux is far lower than the basic modulator sample rate, Fs, or even than Fs/m, where m is the number of analog input channels.
When a sigma delta modulator is used for a TDM ADC, further filtering and decimation is generally required after the output bit stream has been de-multiplexed into multiple TDM bit streams. And when switching from one input signal to the next, the internal analog integrators and the output digital filter all have to settle to appropriate conditions for the new input signal waveform. Typically this settling time is longest for the digital filter.
The settling time of a third-order sinc filter is determined by the first valid value of the order times the decimation rate, e.g., 96 times the modulator sample time. In such a case, the final output data rate would be Fs/m/96. Unless the sampling rate Fs is very high, this final rate can become too low for accurate use in some applications.
A representative embodiment of the present invention includes a multiplexed signal processor having an input circuit for receiving multiple input signals. A modulator processes a selected input signal to produce a representative digital output. The modulator includes an integrator that integrates the difference between the selected input signal and a feedback signal representative of the digital output. A signal control circuit selects in turn by time division multiplexing each input signal for a processing period as the selected input signal, and stores the digital output and the integrator state at the end of each processing period. After an initial processing period for each input signal, each processing period begins based on the digital output and the integrator state from the end of the previous processing period for that input signal.
Another embodiment of the present invention includes a multiplexed signal processor having an input circuit for receiving multiple input signals. A multistage modulator processes a selected input signal to produce a representative digital output. The modulator includes one or more integrator stages. One of the integrator stages includes a separate discrete integrator for each input signal, where each integrator produces an output representing the integration of the discrete integrator input and the discrete integrator output. The other integrator stage includes a time division multiplexed integrator that selects each input signal in turn for a processing period to produce an output representing the integration of the multiplexed integrator input and the multiplexed integrator output. After an initial processing period for each input signal, each processing period begins based on the digital output and multiplexed integrator output from the end of the previous processing period for that input signal.
In an embodiment, the multiple input signals may be either analog or digital signals. A switched capacitor arrangement may store at least one of the digital outputs and the integrator states. The signal processor may be a sigma delta modulator. The signal processor may also include a filter in communication with the modulator for removing noise from the digital output, e.g., a sinc filter.